Phase-locked loops (PLLs) are feedback control systems that are often an essential part of many telecommunications devices. PLLs are used in modulators and demodulators, in frequency synthesizers, in clock synchronizations circuits and in many other high-speed communication applications. PLL can be implemented using digital or analog devices.
FIG. 1 shows a block diagram of a conventional PLL. The PLL shown in FIG. 1 includes four main components, namely, a Phase Frequency Detector (PFD) 11, a Filter 12, a Variable Frequency Oscillator (VFO) 13 and feedback loop with a frequency divider 14. The VFO 13 could for example be a Voltage Controlled Oscillator (VCO).
The PFD 11 compares the phase and frequency of the feedback signal to the reference signal and it generates an error signal indicating any difference it detects. The error signal generated by PFD 11 passes through the filter 12 and is used to adjust the frequency of the VFO 13. Any differences between the input signal and the feedback signal are thus used to change the frequency of the VFO.
A PLL can be used as a frequency multiplier. For example, in the circuit shown in FIG. 1, the output of the reference signal may be a 10 Mhz signal. The output of the VCO may for example be a 1 Ghz signal. In such a PLL the frequency divider 14 would divide the 1 Ghz output signal down to a 10 Mhz signal. The frequency divider 14 can be adjusted to a higher or lower divisor in order to change the output frequency of the PLL.
There is great deal of published literature which describes the design and operation of prior art PLLs. For example, PLL technology is described in a text book entitled “Phase-Locked Loops” by Roland Best, ISBN: 0071412018, dated Jun. 20, 2003. Other books and literature which describe the principles and applications of PLL are also available.
An important parameter which affects the operation of a PLL is the loop “gain”. An important component of loop gain is the gain of the VFO. Gain of a VFO is a measure of the change in the output of the VFO relative to changes in the input signal to the VFO. Where the VFO is a Voltage Controlled Oscillator (a VCO), the gain of the VCO (or of the PLL) is often expressed as mega-hertz per volt (MHz/V). Generally, for a particular PLL, it is desirable to have a constant loop gain over the entire range of frequencies at which the PLL operates. If the loop gain differs at different frequencies, the lock time, the bandwidth, and other parameters of the PLL may change when the operating frequency changes and this may adversely affect the PLL.
In some applications, a PLL must be able to operate over a wide frequency range. In many such applications it is desirable to have a loop gain that does not significantly change as the operating frequency changes even though the frequency changes cover a wide range. The present invention is designed to provide an improved PLL which has substantially constant loop gain over a wide frequency range.